“摩爾定律依然有效但對(duì)于當(dāng)今行業(yè)的大多數(shù)領(lǐng)域已經(jīng)不管用”,
可編程邏輯器件供應(yīng)商賽靈思公司的主席Wim Roelandts如此說(shuō)。Roelandts在訪問(wèn)以色列時(shí)接受了EE Times歐洲版的采訪,此行他參加了最近舉行的全球半導(dǎo)體協(xié)會(huì)大會(huì)。
今年1月,Roelandts從他擔(dān)任的賽靈思公司總裁兼首席執(zhí)行官的角色上升職,成為公司董事會(huì)主席。他1996年被任命為公司總裁兼首席執(zhí)行官,把公司從年銷(xiāo)售額5.6億美元發(fā)展成為2007財(cái)年的18億美元。
目前,公司已經(jīng)任命Moshe Gavrielov擔(dān)任總裁兼首席執(zhí)行官。Gavrielov曾任以色列Verisity有限公司的首席執(zhí)行官,該公司最終在2005年由Cadence公司兼并。Gavrielov已經(jīng)在最近表示,他打算在他的任期內(nèi)把賽靈思發(fā)展成為年銷(xiāo)售收入100億美元的公司。
EE Times:PLD行業(yè)的弱點(diǎn)是什么？
Wim Roelandts: 常見(jiàn)的可編程邏輯芯片比較大且更為昂貴,而這就是為什么我們持續(xù)地推動(dòng)摩爾定律,它對(duì)我們管用,但是,對(duì)于大多數(shù)行業(yè)它已經(jīng)不管用。
如果你設(shè)計(jì)一款調(diào)制解調(diào)器芯片,那么,沒(méi)有必要把它縮小至45納米。需要采用先進(jìn)工藝技術(shù)的應(yīng)用越來(lái)越少,這些工藝技術(shù)僅僅被那些需要非常大量的晶體管的人所使用。那就是為什么在某些應(yīng)用,像汽車(chē)行業(yè),仍然采用180納米和130納米工藝技術(shù)。甚至大多數(shù)消費(fèi)電子設(shè)備并不是采用先進(jìn)的工藝技術(shù),而是180納米、130納米以及90納米工藝技術(shù)。
在過(guò)去的幾年中,可編程邏輯已經(jīng)讓我們繼續(xù)利用摩爾定律,并繼續(xù)驅(qū)動(dòng)成本的降低,因此,摩爾定律開(kāi)始在更多的應(yīng)用中被采用,如消費(fèi)電子應(yīng)用中,舉例來(lái)說(shuō),像平板電視機(jī)、蜂窩電話以及機(jī)頂盒等等。汽車(chē)是另一個(gè)好例子,其中,越來(lái)越多的可編程器件被采用,因?yàn)榭删幊绦缘某杀菊兊迷絹?lái)越低,這要?dú)w功于摩爾定律。因此,在可編程邏輯器件行業(yè),靈活性依然是優(yōu)點(diǎn),缺點(diǎn)就是需要不斷的超越摩爾定律。
可編程邏輯器件的另一個(gè)缺點(diǎn)就是,如果你構(gòu)建一塊較大規(guī)模的芯片,那么,你就需要采用大量的軟件、應(yīng)用軟件、IP以及諸如此類的模塊,從而使設(shè)計(jì)更為復(fù)雜。過(guò)去,FPGA公司提供一顆芯片和一套編譯器,客戶完成一切工作。現(xiàn)在,他們希望獲得更多的IP,這就改變了FPGA公司的運(yùn)營(yíng)方式。我們?cè)趲啄暌郧熬驼J(rèn)識(shí)到這一點(diǎn),因此,我們建立了強(qiáng)大的組織來(lái)為各個(gè)客戶開(kāi)發(fā)IP以及對(duì)IP進(jìn)行集成。
EE Times:對(duì)于當(dāng)今的PLD行業(yè)來(lái)說(shuō),在哪里的機(jī)會(huì)最大？
WR: 最大的機(jī)會(huì)就是讓PLD被應(yīng)用于大批量的市場(chǎng)。當(dāng)我開(kāi)始為賽靈思工作,也就是12年半以前,每年6萬(wàn)片對(duì)我們來(lái)說(shuō)就是大批量了。現(xiàn)在,對(duì)單一型號(hào)的產(chǎn)品,我們每年最大的批量是8百萬(wàn)片,并且它被用于平板電視系統(tǒng)。在未來(lái)的幾年中,我們將進(jìn)入更為大批量的市場(chǎng),特別是高端產(chǎn)品市場(chǎng),而隨著時(shí)間的推移,我們將覆蓋低端大批量產(chǎn)品市場(chǎng)。
第二個(gè)機(jī)會(huì)就是提供更為集成的解決方案。現(xiàn)代的FPGA不再僅僅是可編程邏輯,而是介于ASIC和FPGA之間的混合芯片,它包含微處理器、收發(fā)器以及許多其它單元。我們采用非常先進(jìn)的技術(shù)來(lái)構(gòu)建芯片。在可編程邏輯芯片中加入少量硬核的確不會(huì)大幅增加芯片的尺寸,但是,它極大地提升了價(jià)值。
通過(guò)把諸如存儲(chǔ)器和DSP核這樣的單元集成在芯片上,我們提高了價(jià)值。賽靈思一直在把越來(lái)越多的硬核加入FPGA之中,因?yàn)樗倪M(jìn)性能、提高速度且降低功耗。
ASSP與FPGA的比較
EE Times:在FPGA領(lǐng)域出現(xiàn)了向著低成本發(fā)展的趨勢(shì),從而造成市場(chǎng)上自相殘殺的現(xiàn)象,您對(duì)此怎么看？
WR: 我認(rèn)為那不是威脅,但是,更確切地說(shuō),那是行業(yè)的標(biāo)準(zhǔn)。每?jī)赡昃陀胁捎孟冗M(jìn)技術(shù)的產(chǎn)品上市,它們的成本更低。存儲(chǔ)器的容量一年增加40%,而邏輯單元的數(shù)量一年增加大約70%。
在過(guò)去的幾年中,在邏輯單元的消耗和價(jià)格的下降之間沒(méi)有太多的差異,因此,該行業(yè)的增長(zhǎng)率不是非常大,大約每年為10%。在進(jìn)一步降低價(jià)格和建立新應(yīng)用之間一直存在持續(xù)的戰(zhàn)爭(zhēng)。這是好事情,因?yàn)楫?dāng)價(jià)格快速下降時(shí),我們能夠捕獲新的市場(chǎng),否則的話,就不可能做到這一點(diǎn)。
EE Times:您認(rèn)為ASSP和FPGA相比怎么樣？
WR: ASSP就是ASIC的終極版。現(xiàn)在,被設(shè)計(jì)的ASIC越來(lái)越少,因?yàn)樗婕暗某杀靖咚隆SIC可以由ASSP或PLD所取代。目前,ASSP已經(jīng)取得了非常大的成功,但是,最終它們的確定跟ASIC是一樣的。ASSP被提供給4-5個(gè)客戶,這樣看來(lái),ASIC變得經(jīng)濟(jì)是沒(méi)有理由的,隨著時(shí)間的推移,ASSP也將發(fā)生相同的事情。
越來(lái)越多的公司正在向大批量ASSP轉(zhuǎn)移,因?yàn)槿藗儼l(fā)現(xiàn)投資較小批量的產(chǎn)品從經(jīng)濟(jì)角度來(lái)說(shuō)是沒(méi)有理由的。隨著時(shí)間的推移,ASSP將必須把重點(diǎn)放在較大批量的應(yīng)用上,與此同時(shí),較小批量的應(yīng)用將由PLD所主宰,因?yàn)椴捎肞LD更為經(jīng)濟(jì)。
EE Times:您今年的策略是什么？
WR: 我們打算從軟件、IP以及其它方面考慮提供更為完整的解決方案。ASSP供應(yīng)商提供芯片和軟件并告訴客戶“你把它放在板上就工作了”。為了讓FPGA抓住那個(gè)市場(chǎng),我們必須提供不僅僅是FPGA,而且有比ASSP中硬核工作更快的軟IP,并且我們將確保它在一塊均能工作。這一策略將最終引領(lǐng)我們成為一個(gè)100億美元的公司,然而,這可能要花上10年。
EE Times:你們的競(jìng)爭(zhēng)對(duì)手Altera今年將向40納米轉(zhuǎn)移,從這方面說(shuō),你們有什么計(jì)劃？
WR: 我們正在設(shè)計(jì)40納米的產(chǎn)品。作為主席,我們無(wú)法就產(chǎn)品開(kāi)發(fā)計(jì)劃和付運(yùn)時(shí)間做出承諾,但是,我能夠說(shuō)的就是,在2006年推出了65納米的產(chǎn)品,并且每?jī)赡晡覀儗⑼瞥鲂乱淮漠a(chǎn)品,因此,我把它留給你自己做出結(jié)論。
EE Times:您在兼并方面采取什么策略？
WR: 我們出于技術(shù)原因考慮會(huì)兼并一家公司,而不是為了攫取市場(chǎng)份額。我們分析我們的產(chǎn)品組合以及我們薄弱的領(lǐng)域所在,或者說(shuō),我們?nèi)笔У漠a(chǎn)品所在,然后,我們出手兼并一家公司。
EE Times:您如何看待公司現(xiàn)在的財(cái)務(wù)前景？
WR: 3月份結(jié)束的財(cái)年與去年同期持平。在2006年,我們上半年增長(zhǎng)強(qiáng)勁,而下半年增長(zhǎng)非常慢。然而,我們把去年12個(gè)季度與前年的同期進(jìn)行了比較,我們的增長(zhǎng)率為8%。我認(rèn)為幾年將是比較好的年景。
我們已經(jīng)處于非常強(qiáng)大的地位,因?yàn)槲覀冋谑袌?chǎng)上主推65納米產(chǎn)品,而在高端市場(chǎng),我們的確沒(méi)有競(jìng)爭(zhēng)對(duì)手。
翻頁(yè)查看英文原文:
Executive Interview: Xilinx chairman Wim Roelandts
Moore's Law is still valid but it does not work for most sectors of the industry today, according to Wim Roelandts, chairman of programmable logic device vendor Xilinx Inc. (San Jose, Calif.). Roelandts met EE Times Europe during his first visit to Israel, where he attented the recent Global Semiconductor Association conference.
In January, Roelandts stepped up from his post as president and CEO of Xilinx, to become the company's chairman of the board. Roelandts was named president and CEO in 1996 and grew the company's sales from $560 million to over $1.8 billion in fiscal year 2007.
The company has appointed Moshe Gavrielov president and CEO. Gavrielov was the CEO of Israel-based Verisity Ltd., which was ultimately acquired by Cadence in 2005. Gavrielov has recently stated that he intends to grow Xilinx to a $10 billion revenue company during his tenure.
EE Times : What are the weaknesses of the PLD industry?
Wim Roelandts: The usual programmable logic chips are bigger and more expensive, and this is why we continue to push Moore's law, which works for us, but does not work anymore for most industries.
If you do a modem chip there is no need to shrink it to 45 nanometers. There are fewer and fewer applications that require advanced [process] technologies. These technologies are only used by people who need very large number of transistors. That is why certain applications like automotive are still using 180-nm and 130-nm. Even most consumer devices are not using advanced [process] technologies, but rather 180-nm, 130-nm or maybe 90-nm.
In the last couple of years, programmable logic has allowed us to keep using Moore's Law, and continue to drive costs down, and therefore become used in more applications, such as consumer applications " flat panel TVs, cellphones, set-top boxes, you name it. Automotive is another good example of where more and more programmable devices are used, because the cost of programmability is becoming smaller, thanks to Moore's Law. Therefore, in PLDs the flexibility is still there as an advantage and the disadvantages are outweighed by our use of Moore's Law.
Another weakness of the PLDs is the fact that if you build bigger chips you need a lot more software, applications, IP and so on, which make things more complicated. In the past, FPGA companies supplied a chip and a compiler and the customers did everything by themselves. Now, they expect to get more IP, and this changed the way that FPGA companies operate. We saw this several years ago, and therefore we have a strong organization that develops IP for the customers and does the integration of IP.
EE Times : What are the big opportunities for the PLD industry today?
WR: The big opportunity is to have PLDs used in high volume markets. When I started working for Xilinx, twelve and a half years ago, big volume for us was maybe 60,000 units per year. Today our biggest volume is 8 millions units per year for a single socket, and it is used for a flat panel TV system. Over the years, we will be approaching even higher volume markets, especially in high end products, but with time we will reach low end products with high volume.
The second opportunity is to provide a more integrated solution. A modern FPGA is no longer just programmable logic, but rather a hybrid between an ASIC and an FPGA. It contains processors, transceivers and many other elements. We build the chip in a very advanced technology. Adding a few hard cores to that chip really does not increase the size very much, but it significantly increases the value.
By putting elements such as memories and DSP cores on chips, we increase the value. Xilinx has been adding more and more hard cores into its FPGAs, because it improves the performance and the speed and reduces power consumption.
ASSPs vs FPGAs
EE Times : There is a trend towards low cost FPGAs, causing some cannibalization of the market. Can you refer to that?
WR:I don't consider that as a threat, but more a standard of the industry. Every two years there is a new generation of products in advanced technologies, which cost less. Memory bits grow at about 40 percent a year, while logic cells grow at about 70 percent a year.
In the last couple of years there has not been much difference between the consumption of logic cells and the decline in prices, so the growth rate in the industry has not been very great — about 10 percent per year. There is a continuing battle to lower prices and get new applications. It is an advantage, because when prices go down so quickly, we can capture new markets that otherwise would not have been possible.
EE Times : How do you regard ASSPs as against FPGAs?
WR: ASSPs are the ultimate of the ASICs. Fewer ASICs are designed, because of the costs involved. ASICs can be replaced by an ASSP or a PLD. For the moment, ASSPs have been very successful, but ultimately their drawback is the same as that of an ASIC. An ASSP goes to 4 or 5 customers, so if ASICs become economically not justifiable, the same will happen with ASSPs over time.
More companies are moving to the high volume ASSPs, since people don't find it economically justifiable to invest in smaller volumes. With time, ASSPs will have to focus on the higher volume sockets, while lower volume sockets will be dominated by PLDs, because of economics.
EE Times : What is your strategy for this year?
WR : We intend to provide more complete solutions in terms of software, IP and so on. ASSP vendors provide a chip and software and tell the customer 'you put it on a board and it works'. For FPGAs to capture that segment, we have to provide not just the FPGA but also the soft IP that works much faster than the hard IP in ASSPs, and we'll make sure that it all works together. This strategy will eventually lead us to be a $10 billion company, maybe in 10 years.
EE Times : Your colleagues at Altera will be moving to 40-nm this year. What about your plans in this regard?
WR : We are designing for products in 40-nm. As chairman I cannot give commitments regarding products and shipping, but what I can say is that the 65-nm products were introduced in 2006, and every two years we come out with new generation of products, so I'll leave it to you to make your own conclusions.
EE Times : What is your strategy regarding acquisitions?
WR: We are acquiring companies for technology reasons, not in order to get market share. We look at our portfolio and where we have areas we are weak in, or that we are missing, then we go out and acquire companies.
EE Times : How do you see you financial prospects now?
WR: The fiscal year that ended in March will be about flat compared to the year before. In 2006 we had a very strong first half and a very weak second half. But when we compare our last December quarter to the same quarter a year before, we grew at 8 percent. I think this year will be better.
We are in a very strong position, because we are putting 65-nm products on the market, and in the high end we really have no competition.
